COM20019 Datasheet, PDF (33/81 Pages) SMSC Corporation – Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM

BIT
BIT NAME
7-3 Reserved
2,1,0 Sub Address 2,1,0
Table 9 - Sub Address Register
SYMBOL
DESCRIPTION
These bits are undefined.
SUBAD
2,1,0
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD2
0
0
0
0
1
1
1
1
SUBAD1 SUBAD0 Register
0
0 Tentative ID \ (Same
0
1 Node ID
\ as in
1
0 Setup 1 / Config
1
1 Next ID / Register)
0
0 Setup 2
0
1 Reserved
1
0 Reserved
1
1 Reserved
SUBAD1 and SUBAD0 are exactly the same as exist in the
Configuration Register. SUBAD2 is cleared automatically by
writing the Configuration Register.
7 Reset
6 Command
Chaining Enable
5 Transmit Enable
Table 10 - Configuration Register
RESET
A software reset of the COM20019 is executed by writing a
logic "1" to this bit. A software reset does not reset the
microcontroller interface mode, nor does it affect the
Configuration Register. The only registers that the software
reset affect are the Status Register, the Next ID Register, and
the Diagnostic Status Register. This bit must be brought
back to logic "0" to release the reset.
CCHEN
This bit, if high, enables the Command Chaining operation of
the device. Please refer to the Command Chaining section
for further details. A low level on this bit ensures software
compatibility with previous SMSC ARCNET devices.
TXEN
When low, this bit disables transmissions by keeping
nPULSE1, nPULSE2 if in non-Backplane Mode, and nTXEN
pin inactive. When high, it enables the above signals to be
activated during transmissions. This bit defaults low upon
reset. This bit is typically enabled once the Node ID is
determined, and never disabled during normal operation.
Please refer to the Improved Diagnostics section for details
on evaluating network activity.
33
DISCONTINUED DATASHEET