COM20019 Datasheet, PDF (36/81 Pages) SMSC Corporation – Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM

BIT
BIT NAME
7 Read Bus Timing
Select
6,5,4 Reserved
3 Enhanced
Functions
2 No Synchronous
1,0 Reconfiguration
Timer 1, 0
Table 12 - Setup 2 Register
SYMBOL
DESCRIPTION
RBUSTMG This bit is used to Disable/Enable the High Speed CPU
Read function for High Speed CPU bus support.
RBUSTMG=0: Disable (Default), RBUSTMG=1: Enable. It
does not influence write operation. High speed CPU Read
operation is only for non-multiplexed bus.
These bits are undefined.
EF
This bit is used to enable the new enhanced functions in the
COM20019. EF = 0: Disable (Default), EF = 1: Enable. If EF
= 0, the timing and function is the same as in the
COM20020, Revision B. See appendix “A”. EF bit must be
‘1’ if the data rate is over 5Mbps.
EF bit should be ‘1’ for new design customers.
EF bit should be ‘0’ for replacement customers.
NOSYNC This bit is used to enable the SYNC command during
initialization. NOSYNC= 0, Enable (Default) The line must
be idle for the RAM initialization sequence to be written.
NOSYNC= 1, Disable:) The line does not have to be idle for
the RAM initialization sequence to be written. See appendix
“A”.
RCNTM1,0 These bits are used to program the reconfiguration timer as a
function of maximum node count. These bits set the time out
period of the reconfiguration timer as shown below. The
time out periods shown are for 312.5 Kbps.
RCNTM1 RCNTM0
Time Out
Max Node Count
Period
0
0
6.72 S
Up to 255 nodes
0
1
1.68 S
Up to 64 nodes
1
0
840 mS
Up to 32 nodes
1
1
420 mS* Up to 16 nodes
Note*: The node ID value 255 must exist in the network for
420 mS timeout to be valid.
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