COM20019 Datasheet, PDF (59/81 Pages) SMSC Corporation – Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM

FIGURE 12 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE
AD0-AD2,
D3-D7
nCS
ALE
nWR
nRD
VALID
t1
t2,
t4
t3
t9
t5
t13 ^{Note 3}
VALID DATA
t10
t6
t11
t7
Note 2
t8**
t12
t8
Parameter
min
max units
t1 Address Setup to ALE Low
20
nS
t2 Address Hold from ALE Low
10
nS
t3 nCS Setup to ALE Low
10
nS
t4 nCS Hold from ALE Low
10
nS
t5 ALE Low to nDS Low
15
nS
t6 Valid Data Setup to nDS High
30
nS
t7 Data Hold from nDS High
10
nS
t8 Cycle Time (nWR to Next )**
4TARB*
nS
t9 _{ALE High Width}
t10 ALE Low Width
t11 nWR Low Width
t12 nWR High Width
t13 nRD to nWR Low
20
nS
20
nS
20
nS
20
nS
20
nS
* _{TARB is the Arbitration Clock Period}
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
Note 1: The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
** Note 2: _{Any cycle occurring after a write to Address Pointer Low Register requires a}
minimum of 4TARB from the trailing edge of nWR to the leading edge of the
next nWR.
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
59
Note 3: _{Write cycle for Address Pointer Low Register occurring after a read from Data}
DISCONTINUED DATASHEET ^{Register requires a minimum of 5TARB from the trailing edge of nRD to the}
leading edge of nWR.