COM20019 Datasheet, PDF (69/81 Pages) SMSC Corporation – Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM

nTXEN
t1
nPULSE1
nPULSE2
(Internal Clk)
t9
t4
t3
t2
t5
t6
t7
t13
t8
LAST BIT
(3200 nS BIT TIME)
RXIN
t10
t12
t11
Parameter
t1 nPULSE2 High to nTXEN Low
t2 _{nPULSE1 Pulse Width}
t3 _{nPULSE1 Period}
t4 _{nPULSE2 Low to nPULSE1 Low}
t5 _{nPULSE2 High Time}
t6 _{nPULSE2 Low Time}
t7 _{nPULSE2 Period}
t8 nPULSE2 High to nTXEN High
(First Rising Edge on nPULSE2 after Last Bit Time)
t9 nTXEN Low to first nPULSE1 Low**
t13 Beginning Last Bit Time to nTXEN High**
t10 _{RXIN Active Pulse Width}
t11 _{RXIN Period}
t12 _{RXIN Inactive Pulse Width}
Above values are for 312.5 Kbps.
Other Data Rates are shown below.
TDR is the Data Rate Period
*t5, t6 = TDR/4
*t2, t7, t10 = TDR/2
*t3, t11 = TDR
**t9
=
7
4
x
TDR
+/-
100
nS
**t13
=
5
4
x
TDR
+/-
100
nS
69
min typ max
-25
50
1600*
3200*
-25
50
800*
800*
1600*
-25
50
units
nS
nS
nS
nS
nS
nS
nS
nS
5500
3900
5700 nS
4100 nS
10 1600*
nS
3200*
nS
20
nS
DISCONTINUED DATASHEET