LAN91C100FD_0601 Datasheet, PDF (59/78 Pages) SMSC Corporation – FEAST Fast Ethernet Controller with Full Duplex Capability

FEAST Fast Ethernet Controller with Full Duplex Capability
7.3 High End ISA or Non-Burst EISA Machines
On ISA machines, the LAN91C100FD is accessed as a 16 bit peripheral. No support for XT (8 bit
peripheral) is provided. The signal connections are listed in the following table:
Table 7.2 - High-End ISA or Non-Burst EISA Machines Signal Connectors
ISA BUS
SIGNAL
A1-A15
AEN
nIORD
nIOWR
IOCHRDY
RESET
A0
nSBHE
IRQn
D0-D15
LAN91C100FD
SIGNAL
A1-A15
AEN
nRD
nWR
ARDY
RESET
nBE0
nBE1
INTR0-INTR3
D0-D15
NOTES
Address bus used for I/O space and register decoding.
Qualifies valid I/O decoding - enabled access when low.
I/O Read strobe - asynchronous read accesses. Address is valid
before leading edge.
I/O Write strobe - asynchronous write access. Address is valid
before leading edge. Data is latched on trailing edge.
This signal is negated on leading nRD, nWR if necessary. It is
then asserted on CLK rising edge after the access condition is
satisfied.
16 bit data bus. The bus byte(s) used to access the device are a
function of nBE0 and nBE1:
nBE0
0
0
1
nBE1
0
1
0
D0-D7
Lower
Lower
Not used
D8-D15
Upper
Not used
Upper
nIOCS16
GND
VCC
nLDEV buffered
LCLK nADS
nBE2 nBE3
nCYCLE W/nR
nRDYRTN
Not used = tri-state on reads, ignored on writes
nLDEV is a totem pole output. Must be buffered using an open
collector driver. nLDEV is active on valid decodes of A15-A4 and
AEN=0.
UNUSED PINS
No upper word access.
SMSC DS – LAN91C100FD Rev. D
Page 59
DATASHEET
Rev. 01-20-06