LAN91C100FD_0601 Datasheet, PDF (15/78 Pages) SMSC Corporation – FEAST Fast Ethernet Controller with Full Duplex Capability

FEAST Fast Ethernet Controller with Full Duplex Capability
Chapter 4 Functional Description
4.1 Description of Block
4.1.1 Clock Generator Block
1. The XTAL1 and XTAL2 pins are to be connected to a 25 MHz crystal.
2. TXCLK and RXCLK are 10 MHz clock inputs. These clocks are generated by the external ENDEC in 10 Mbps
mode and are only used by the CSMA/CD block.
3. TX25 is an input clock. It will be the nibble rate of the particular PHY connected to the MII (2.5 MHz for a 10
Mbps PHY, and 25 MHz for a 100 Mbps PHY).
4. RX25 - This is the MII nibble rate receive clock used for sampling received data nibbles and running the receive
state machine. (2.5 MHz for a 10 Mbps PHY, and 25 MHz for a 100 Mbps PHY).
5. LCLK - Bus clock - Used by the BIU for synchronous accesses. Maximum frequency is 50 MHz for VL BUS
mode, and 8.33 MHz for EISA slave DMA.
4.2
CSMA/CD BLOCK
This is a 16 bit oriented block, with fully- independent Transmit and Receive logic. The data path in and out
of the block consists of two 16-bit wide uni-directional FIFOs interfacing the DMA block. The DMA port of
the FIFO stores 32 bits to exploit the 32 bit data path into memory, but the FIFOs themselves are 16 bit
wide. The Control Path consists of a set of registers interfaced to the CPU via the BIU.
4.2.1 DMA Block
This block accesses packet memory on the CSMA/CD’s behalf, fetching transmit data and storing received
data. It interfaces the CSMA/CD Transmit and Receive FIFOs on one side, and the Arbiter block on the
other. To increase the bandwidth into memory, a 50 MHz clock is used by the DMA block, and the data
path is 32 bits wide.
For example, during active reception at 100 Mbps, the CSMA/CD block will write a word into the Receive
FIFO every 160ns. The DMA will read the FIFO and accumulate two words on the output port to request a
memory cycle from the Arbiter every 320ns.
DMA will discard a packet if nRXDISC is asserted for a minimum of 80ns during a reception. If asserted
late, the DMA will receive the packet normally. The nRXDISC is defined valid for the DMA interface for as
long as the RCVDMA signal is active.
The DMA machine is able to support full duplex operation. Independent receive and transmit counters are
used. Transmit and receive cycles are alternated when simultaneous receive and transmit accesses are
needed.
4.2.2 Arbiter Block
The Arbiter block sequences accesses to packet RAM requested by the BIU and by the DMA blocks. BIU
requests represent pipelined CPU accesses to the Data Register, while DMA requests represent
CSMA/CD data movement. The external memory used is a 25ns SRAM.
SMSC DS – LAN91C100FD Rev. D
Page 15
DATASHEET
Rev. 01-20-06