LAN91C100FD_0601 Datasheet, PDF (16/78 Pages) SMSC Corporation – FEAST Fast Ethernet Controller with Full Duplex Capability

FEAST Fast Ethernet Controller with Full Duplex Capability
The Arbiter is also responsible for controlling the nRWE0-nRWE3 lines as a function of the bytes being
written. Read accesses are always 32 bit wide, and the Arbiter steers the appropriate byte(s) to the
appropriate lanes as a function of the address.
The CPU Data Path consists of two uni-directional FIFOs mapped at the Data Register location. These
FIFOs can be accessed in any combination of bytes, word, or doublewords. The Arbiter will indicate 'Not
Ready' whenever a cycle is initiated that cannot be satisfied by the present state of the FIFO.
4.2.3 MMU Block
The Hardware Memory Management Unit allocates memory and transmit and receive packet queues. It
also determines the value of the transmit and receive interrupts as a function of the queues. The page size
is 2k, with a maximum memory size of 128k. MIR and MCR values are interpreted in 512 byte units.
4.2.4 BIU Block
The Bus Interface Unit can handle synchronous as well as asynchronous buses; different signals are used
for each one. Transparent latches are added on the address path using rising nADS for latching.
When working with an asynchronous bus like ISA, the read and write operations are controlled by the
edges of nRD and nWR. ARDY is used for notifying the system that it should extend the access cycle. The
leading edge of ARDY is generated by the leading edge of nRD or nWR while the trailing edge of ARDY is
controlled by the internal LAN91C100FD clock and, therefore, asynchronous to the bus.
In the synchronous VL Bus type mode, nCYCLE and LCLK are used to for read and write operations.
Completion of the cycle may be determined by using nSRDY. nSRDY is controlled by LCLK and
synchronous to the bus.
Direct 32 bit access to the Data Path is supported by using the nDATACS input. By asserting nDATACS,
external DMA type of devices will bypass the BIU address decoders and can sequentially access memory
with no CPU intervention. nDATACS accesses can be used in the EISA DMA burst mode (nVLBUS=1) or
in asynchronous cycles. These cycles MUST be 32 bit cycles. Please refer to the corresponding timing
diagrams for details on these cycles.
The BIU is implemented using the following principles:
4.2.5 MAC-PHY Interface Block
Two separate interfaces are defined, one for the 10 Mbps bit rate interface and one for the MII 100 Mbps
and 10 Mbps nibble rate interface. The 10 Mbps ENDEC interface comprises the signals used for
interfacing Ethernet ENDECs. The 100 Mbps interface follows the MII for 100 Mbps 802.3 networks
proposal, and it is based on transferring nibbles between the MAC and the PHY.
For the MII interface, transmit data is clocked out using the TX25 clock input, while receive data is clocked
in using RX25.
In 100 Mbps mode, the LAN91C100FD provides the following interface signals to the PHY:
ƒ For transmission: TXEN100 TXD0-3 TX25
ƒ For reception: RX_DV RX_ER RXD0-3 RX25
ƒ For CSMA/CD state machines: CRS100 COL100
A transmission begins by TXEN100 going active (high), and TXD0-TXD3 having the first valid preamble
nibble. TXD0 carries the least significant bit of the nibble (that is the one that would go first out of the EPH
Rev. 01-20-06
Page 16
DATASHEET
SMSC DS – LAN91C100FD Rev. D