COM20022I Datasheet, PDF (52/83 Pages) SMSC Corporation – 10 MBPS ARCNET CONTROLLER WITH 2KX8 ON BOARD RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
the COM20022I deposits packets into the RAM buffer in the same format that the transmitting node arranges
them, which allows for a message to be received and then retransmitted without rearranging any bytes in the
RAM buffer other than the SID and DID. Once the packet is received and stored correctly in the selected
buffer, the COM20022I sets the RI bit to logic "1" to signal the microcontroller that the reception is complete.
MSB
TRI
RI
TRI
LSB
TA
POR
TEST RECON
TMA
TTA
TMA
TTA
6.7
Figure 6.4 - Command Chaining Status Register Queue
Command Chaining
The Command Chaining operation allows consecutive transmissions and receptions to occur without host
microcontroller intervention.
Through the use of a dual two-level FIFO, commands to be transmitted and received, as well as the status
bits, are pipelined.
In order for the COM20022I to be compatible with previous SMSC ARCNET device drivers, the device
defaults to the non-chaining mode. In order to take advantage of the Command Chaining operation, the
Command Chaining Mode must be enabled via a logic "1" on bit 6 of the Configuration Register.
In Command Chaining, the Status Register appears as in Figure 6.4.
The following is a list of Command Chaining guidelines for the software programmer. Further detail can be
found in the Transmit Command Chaining and Receive Command Chaining sections.
The device is designed such that the interrupt service routine latency does not affect performance.
Up to two outstanding transmissions and two outstanding receptions can be pending at any given
time. The commands may be given in any order.
Up to two outstanding transmit interrupts and two outstanding receive interrupts are stored by the
device, along with their respective status bits.
The Interrupt Mask bits act on TTA (Rising Transition on Transmitter Available) for transmit operations
and TRI (Rising Transition of Receiver Inhibited) for receive operations. TTA is set upon completion
of a packet transmission only. TRI is set upon completion of a packet reception only. Typically there is
no need to mask the TTA and TRI bits after clearing the interrupt.
The traditional TA and RI bits are still available to reflect the present status of the device.
6.7.1 Transmit Command Chaining
When the processor issues the first "Enable Transmit to Page fnn" command, the COM20022I responds in
the usual manner by resetting the TA and TMA bits to prepare for the transmission from the specified
page. The TA bit can be used to see if there is currently a transmission pending, but the TA bit is really
meant to be used in the non-chaining mode only. The TTA bits provide the relevant information for the
device in the Command Chaining mode. In the Command Chaining Mode, at any time after the first
command is issued, the processor can issue a second "Enable Transmit from Page fnn" command. The
COM20022I stores the fact that the second transmit command was issued, along with the page number.
Rev. 08-18-03
Page 52
DATASHEET
SMSC COM20022I