COM20022I Datasheet, PDF (22/83 Pages) SMSC Corporation – 10 MBPS ARCNET CONTROLLER WITH 2KX8 ON BOARD RAM

DREQ
nWR
DMAEN bit
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
minimum 4TARB
Writing Address
Pointer Low
TARB is the ARBITRATION Clock Period. It depends on the TOPR and
SLOW-ARB bit. TOPR is the period of operation clock frequency (output
of the clock multiplier). It depends on the CKUP1 and CKUP0 bits.
TARB = TOPR @ SLOW-ARB = 0
TARB = 2 TOPR @ SLOW-ARB = 1
Figure 5.3 - DREQ Pin First Assertion Timing for All DMA Modes
As an example of gating by cycle, in an ISA bus system, the Refresh period is 15µS. Continuous transfer
by DMA must be less than 15µS to prevent blocking by the Refresh cycle. A DMA cycle of consecutive
DMA cycles is approximately 1uS. The DMA overhead time is approximately 2.5µS. The Refresh
execution time is 500nS. This computes to 15µS - 2.5µS - 500nS = 12µS or 12 cycles. Therefore the
DREQ pin must be negated every 12 cycles. Figure 5.4 illustrates the rough timing of the Programmable-
Burst mode DMA transfer.
Rev. 08-18-03
Page 22
DATASHEET
SMSC COM20022I