COM20022I Datasheet, PDF (29/83 Pages) SMSC Corporation – 10 MBPS ARCNET CONTROLLER WITH 2KX8 ON BOARD RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
5.2.3 Differential Driver Configuration
The Differential Driver Configuration is a special case of the Backplane Mode. It is a dc coupled
configuration recommended for applications like car-area networks or other cost-sensitive applications
which do not require direct compatibility with existing ARCNET nodes and do not require isolation. The
Differential Driver Configuration cannot communicate directly with nodes utilizing the Traditional Hybrid
Configuration. Like the Backplane Configuration, the Differential Driver Configuration does not isolate the
node from the media.
The Differential Driver interface includes a RS485 Driver/Receiver to transfer the data between the cable
and the COM20022I. The nPULSE1 signal transmits the data, provided the Transmit Enable signal is
active. The nPULSE1 signal issues a 200nS (at 2.5Mbps) negative pulse to transmit a logic "1". Lack of
pulse indicates a logic "0". The RXIN signal receives the data, the transmitter portion of the COM20022I is
disabled during reset and the nPULSE1, nPULSE2 and nTXEN pins are inactive.
5.2.4 Programmable TXEN Polarity
To accommodate transceivers with active high ENABLE pins, the COM20022I contains a programmable
TXEN output. To program the TXEN pin for an active high pulse, the nPULSE2 pin should be connected
to ground. To retain the normal active low polarity, nPULSE2 should be left open. The polarity
determination is made at power on reset and is valid only for Backplane Mode operation. The nPULSE2
pin should remain grounded at all times if an active high polarity is desired.
A0/nMUX
A1
A2/BALE
nIOCS16
AD0-AD2,
D3-D15
ADDRESS
DECODING
CIRCUITRY
2K x 8
RAM
ADDITIONAL
REGISTERS
nINTR
nRESET
STATUS/
COMMAND
REGISTER
RESET
LOGIC
MICRO-
SEQUENCER
AND
WORKING
REGISTERS
TX/RX
LOGIC
nRD/nDS
nWR/DIR
nCS
BUS
ARBITRATION
CIRCUITRY
RECONFIGURATION
TIMER
OSCILLATOR
NODE ID
LOGIC
nPULSE1
nPULSE2
nTXEN
RXIN
XTAL1
XTAL2
DMA
DREQ
nDACK
TC
nREFEX
Figure 5.10 - Internal Block Diagram
SMSC COM20022I
Page 29
DATASHEET
Rev. 08-18-03