COM20022I Datasheet, PDF (5/83 Pages) SMSC Corporation – 10 MBPS ARCNET CONTROLLER WITH 2KX8 ON BOARD RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
6.6.3 Receive Sequence ..............................................................................................................................51
6.7 Command Chaining....................................................................................................................................52
6.7.1 Transmit Command Chaining .............................................................................................................52
6.7.2 Receive Command Chaining ..............................................................................................................53
6.8 Reset Details ..............................................................................................................................................54
6.8.1 Internal Reset Logic ............................................................................................................................54
6.9 Initialization Sequence ...............................................................................................................................54
6.9.1 Bus Determination...............................................................................................................................54
6.10 Improved Diagnostics .............................................................................................................................55
6.10.1 Normal Results: ...............................................................................................................................55
6.10.2 Abnormal Results: ...........................................................................................................................56
6.11 Oscillator.................................................................................................................................................56
Chapter 7 Operational Description........................................................................................................ 57
7.1 Maximum Guaranteed Ratings* .................................................................................................................57
7.2 DC Electrical Characteristics......................................................................................................................57
Chapter 8 Timing Diagrams .................................................................................................................. 60
Chapter 9 Package Outline ................................................................................................................... 79
Chapter 10 Appendix A ........................................................................................................................... 80
10.1 NOSYNC Bit ...........................................................................................................................................80
10.2 EF Bit......................................................................................................................................................80
Chapter 11 Appendix B: Example of Interface Circuit Diagram to ISA Bus........................................... 83
List of Figures
Figure 2.1 - COM20022I Pin Configuration ....................................................................................................................8
Figure 3.1 - COM20022I Operation..........................................................................................................................11
Figure 5.1 - Multiplexed, 8051-Like Bus Interface with RS-485 Interface ............................................................18
Figure 5.2 - Non-Multiplexed, 6801-Like Bus Interface with RS-485 Interface ....................................................19
Figure 5.3 - DREQ Pin First Assertion Timing for All DMA Modes ...............................................................................22
Figure 5.4 - Programmable Burst Mode DMA Transfer (Rough Timing) ............................................................23
Figure 5.5 - Non-Burst Mode DMA Data Transfer Rough Timing.................................................................................24
Figure 5.6 - Burst Mode DMA Data Transfer Rough Timing ................................................................................24
Figure 5.7 - High Speed CPU Bus Timing - Intel CPU Mode...............................................................................26
Figure 5.8 - COM20022I Network Using RS-485 Differential Transceivers .........................................................28
Figure 5.9 - Dipulse Waveform for Data of 1-1-0 ....................................................................................................28
Figure 5.10 - Internal Block Diagram ........................................................................................................................29
Figure 6.1 - Illustration of the Effect of RTRG Bit on DMA Timing ......................................................................37
Figure 6.2 - Sequential Access Operation ...............................................................................................................47
Figure 6.3 - RAM Buffer Packet Configuration .............................................................................................................50
Figure 6.4 - Command Chaining Status Register Queue .............................................................................................52
Figure 8.1 - Multiplexed Bus, 68XX-Like Control Signals; Read Cycle ..............................................................60
Figure 8.2 - Multiplexed Bus, 80XX-Like Control Signals; Read Cycle ..............................................................61
Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals Write Cycle ...............................................................62
Figure 8.4 - Multiplexed Bus, 80XX-Like Control Signals; Write Cycle ..............................................................63
Figure 8.5 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle .....................................................64
Figure 8.6 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle .....................................................65
Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle .....................................................66
Figure 8.8 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle .....................................................67
Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.................................................................68
Figure 8.10 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle ...............................................................69
Figure 8.11 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle....................................................70
Figure 8.12 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle ...............................................................71
Figure 8.13 - Normal Mode Transmit or Receive Timing..............................................................................................72
Figure 8.14 - Backplane Mode Transmit or Receive Timing ........................................................................................73
Figure 8.15 - TTL Input Timing on XTAL1 Pin........................................................................................................74
Figure 8.16 - Reset and Interrupt Timing ................................................................................................................74
SMSC COM20022I
Page 5
DATASHEET
Rev. 08-18-03