COM20022I Datasheet, PDF (46/83 Pages) SMSC Corporation – 10 MBPS ARCNET CONTROLLER WITH 2KX8 ON BOARD RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
BIT
BIT NAME
SYMBOL
DESCRIPTION
1,0 Reconfiguration Timer RCNTM1,0 These bits are used to program the reconfiguration timer as a
1, 0
function of maximum node count. These bits set the time out period
of the reconfiguration timer as shown below. The time out periods
shown are for 10 Mbps.
RCNTM1 RCNTM0 Time Out Period Max Node Count
0
0
210 mS
Up to 255 nodes
0
1
52.5 mS
Up to 64 nodes
1
0
26.25 mS
Up to 32 nodes
1
1
13.125 mS*
Up to 16 nodes
Note*: The node ID value 255 must exist in the network for 13.125
mS timeout to be valid.
Table 6.12 - Bus Control Register
BIT
BIT NAME
SYMBOL
DESCRIPTION
7 16 Bit Access
W16
This bit is used to Disable/Enable the 16 bit access. It influences
both CPU cycle and DMA cycle. W16= 0: Disable (Default); W16=
1: Enable
6 Reserved
This bit is undefined.
5 Internal Terminal
Counter Enable;
Re-Trigger mode
ITCEN/
RTRG
The function of this bit is mode dependent. ITCEN is for Non-Burst
or Burst mode. RTRG is for the two Programmable-Burst modes.
ITCEN = 0: Terminate the DMA only by External TC. ITCEN = 1:
Terminate the DMA by Internal or External TC.
RTRG = 0: External Re-Trigger mode; Negated DREQ pin is Re-
asserted by falling edge of nREFEX pin. RTRG = 1: Internal Re-
Trigger mode; Negated DREQ pin is Re-asserted by timeout of
internal gate timer (350ns/750ns).
4 Terminal Count
TC8/
Bit 8
RSYN/
Refresh Synchronous GTTM
Gate Time
The function of this bit is mode dependent. TC8 is for Non-burst or
burst mode. RSYN and GTTM are for the two Programmable-Burst
modes. RSYN is for External Re-Trigger mode. GTTM is for internal
Re-Trigger mode.
Non-burst or burst mode:
TC8: Bit 8 (MSB) of 9 bit Terminal Count setting register. The other
8 bits are in the DMA Count register. Terminal Count setting register
is ignored when ITCEN = 0.
Programmable-Burst and External Re-Trigger mode:
RSYN = 0: DMA is started Immediately.
RSYN = 1: DMA is started after Refresh execution.
Programmable-Burst and Internal Re-Trigger mode:
GTTM = 0: Gate Time is 350nS (min)
GTTM = 1: Gate Time is 750nS (min)
3,2 DMA Transfer Mode DMAMD1,D These bits select the data transfer mode of the DMA. These transfer
MAMD0
modes influence the timing of asserting/negating the DREQ pin.
DMAMD1 DMAMD0
Transfer Mode
0
0
Non-Burst (Default)
0
1
Burst
1
0
Programmable-Burst by Timer
1
1
Programmable-Burst by Cycle Counter
1 TC Polarity
TCPOL
This bit sets the Active polarity of TC pin.
TCPOL = 0: Active High (Default), TCPOL = 1 Active Low
0 DREQ Polarity
DRQPOL This bit sets the Active polarity of DREQ pin.
DRQPOL = 0: Active High (Default), DRQPOL = 1 Active Low
Rev. 08-18-03
Page 46
DATASHEET
SMSC COM20022I