LAN9221 Datasheet, PDF (46/151 Pages) SMSC Corporation – High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
Note 3.16 The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the
setting of PME_EN.
A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the
LAN9221/LAN9221i to the D0 state and will reset the PM_MODE field to the D0 state. As noted above,
the host is required to check the READY bit and verify that it is set before attempting any other reads
or writes of the device. Before the LAN9221/LAN9221i is fully awake from this state the EDPWRDOWN
bit in register 17 of the PHY must be cleared in order to wake the PHY. Do not attempt to clear the
EDPWRDOWN bit until the READY bit is set. After clearing the EDPWRDOWN bit the
LAN9221/LAN9221i is ready to resume normal operation. At this time the WUPS field can be cleared.
Device
BLOCK
PHY
MAC Power
Management
MAC and Host
Interface
Internal Clock
Table 3.10 Power Management States
D0
(NORMAL OPERATION)
Full ON
Full ON
Full ON
D1
(WOL)
Full ON
RX Power Mgmt. Block
On
OFF
D2
(ENERGY DETECT)
Energy Detect Power-Down
OFF
OFF
Full ON
Full ON
OFF
KEY
CLOCK ON
BLOCK DISABLED – CLOCK ON
FULL OFF
Revision 2.6 (12-04-08)
46
DATASHEET
SMSC LAN9221/LAN9221i