LAN9221 Datasheet, PDF (40/151 Pages) SMSC Corporation – High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
If an operation is attempted, and an EEPROM device does not respond within 30mS, the
LAN9221/LAN9221i will timeout, and the EPC timeout bit (EPC_TO) in the E2P_CMD register will be
set.
Figure 3.4, "EEPROM Access Flow Diagram" illustrates the host accesses required to perform an
EEPROM Read or Write operation.
EEPROM Write
Idle
EEPROM Read
Idle
Write Data
Regis ter
Write
Command
Re gis te r
W r ite
Command
Regis ter
Busy Bit = 0
Read
Command
Regis ter
Read
Command
Re gis te r
Busy Bit = 0
Read Data
Re gis te r
Figure 3.4 EEPROM Access Flow Diagram
The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is
disabled, the EEDIO and ECLK signals can be used as general-purpose outputs, or they may be used
to monitor internal MII signals.
3.9.2.1
Supported EEPROM Operations
The EEPROM controller supports the following EEPROM operations under host control via the
E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A
description and functional timing diagram is provided below for each operation. Please refer to the
E2P_CMD register description in Section 5.3.23, "E2P_CMD – EEPROM Command Register," on
page 103 for E2P_CMD field settings for each command.
Revision 2.6 (12-04-08)
40
DATASHEET
SMSC LAN9221/LAN9221i