LAN9221 Datasheet, PDF (129/151 Pages) SMSC Corporation – High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
6.2.1 Special Restrictions on Back-to-Back Write/Read Cycles
It is important to note that there are specific restrictions on the timing of back-to-back write-read
operations. These restrictions concern reading the control registers after any write cycle to the
LAN9221/LAN9221i device. In many cases there is a required minimum delay between writing to the
LAN9221/LAN9221i, and the subsequent side effect (change in the control register value). For
example, when writing to the TX Data FIFO, it takes up to 135ns for the level indication to change in
the TX_FIFO_INF register.
In order to prevent the host from reading stale data after a write operation, minimum wait periods must
be enforced. These periods are specified in Table 6.1, "Read After Write Timing Rules". The host
processor is required to wait the specified period of time after any write to the LAN9221/LAN9221i
before reading the resource specified in the table. These wait periods are for read operations that
immediately follow any write cycle. Note that the required wait period is dependant upon the register
being read after the write.
Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the
minimum write-to-read timing restriction is met. Table 6.1 also shows the number of dummy reads that
are required before reading the register indicated. The number of BYTE_TEST reads in this table is
based on the minimum timing for Tcycle (45ns). For microprocessors with slower busses the number
of reads may be reduced as long as the total time is equal to, or greater than the time specified in the
table. Note that dummy reads of the BYTE_TEST register are not required as long as the minimum
time period is met.
Table 6.1 Read After Write Timing Rules
REGISTER NAME
ID_REV
IRQ_CFG
INT_STS
INT_EN
BYTE_TEST
FIFO_INT
RX_CFG
TX_CFG
HW_CFG
RX_DP_CTRL
RX_FIFO_INF
TX_FIFO_INF
PMT_CTRL
GPIO_CFG
GPT_CFG
GPT_CNT
WORD_SWAP
FREE_RUN
MINIMUM WAIT TIME FOR READ
FOLLOWING ANY WRITE CYCLE
(IN NS)
0
135
90
45
0
45
45
45
45
45
0
135
315
45
45
135
45
180
NUMBER OF BYTE_TEST
READS
(ASSUMING T_CYCLE OF 45NS)
0
3
2
1
0
1
1
1
1
1
0
3
7
1
1
3
1
4
SMSC LAN9221/LAN9221i
129
DATASHEET
Revision 2.6 (12-04-08)