SI598 Datasheet, PDF (9/28 Pages) Silicon Laboratories – Programmable with 28 parts per trillion frequency resolution

Si598/Si599
Table 7. CLK± Output Period Jitter
(Typical values TA = 25 ºC, V_DD = 3.3 V unless otherwise noted)
Parameter
Symbol
Test Condition
Min
Typ
Period Jitter*
J_PER
RMS
Peak-to-Peak
—
3
—
35
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles.
Max Units
—
ps
—
ps
Table 8. CLK± Output Phase Noise (Typical, Si599)
(Typical values TA = 25 ºC, V_DD = 3.3 V)
Offset Frequency
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
74.25 MHz
185 ppm/V
LVPECL
–77
–101
–121
–134
–149
–151
–150
148.5 MHz
185 ppm/V
LVPECL
–68
–95
–116
–128
–144
–147
–148
155.52 MHz
95 ppm/V
LVPECL
–77
–101
–119
–127
–144
–147
–148
Units
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Table 9. Power Supply Noise Rejection
(Typical values TA = 25 ºC, V_DD = 3.3 V)
Parameter
Symbol Test Condition Min
RMS Additive Jitter due to Power Supply Noise*
100 kHz
—
300 kHz
—
φ_PSRR
700 kHz
—
1 MHz
—
*Note: Measured with 100 mVp-p sinusoid applied to power supply pin. VDD = 3.3 V, LVPECL.
Typ
0.32
0.36
0.36
0.32
Max Units
—
ps
—
ps
—
ps
—
ps
Table 10. Spurious Performance
(Typical values TA = 25 ºC, V_DD = 3.3 V)
Parameter
Spurious Free Dynamic Range
Notes:
1. 10 to 160 MHz.
2. 10 to 810 MHz.
Symbol
SFDR
Test Condition
LVPECL, LVDS, CML¹
LVPECL, LVDS, CML²
CMOS¹
Min Typ Max Units
—
75 — dB
—
64 — dB
—
77 — dB
Rev. 1.0
9