SI598 Datasheet, PDF (8/28 Pages) Silicon Laboratories – Programmable with 28 parts per trillion frequency resolution

Si598/Si599
Table 5. CLK± Output Phase Jitter (Si598)
(Typical values TA = 25 ºC, V_DD = 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless otherwise
noted)
Parameter
Symbol
Test Condition
Min Typ Max Units
Phase Jitter (RMS Random)
LVPECL/LVDS/CML¹ —
0.5
—
ps
12 kHz to 20 MHz Integration Bandwidth
CMOS 3.3 V²
—
0.6
—
ps
Phase Jitter (RMS Random)
φ_{J-RANDOM LVPECL/LVDS/CML1}
—
0.3
—
ps
1.875 to 20 MHz Integration Bandwidth
CMOS 3.3 V²
—
0.5
—
ps
Phase Jitter (RMS)
LVPECL/LVDS/CML¹ —
0.5
1
ps
12 kHz to 20 MHz Integration Bandwidth
CMOS 3.3 V²
—
0.6
1
ps
Phase Jitter (RMS)
φ_J
LVPECL/LVDS/CML¹ —
0.5
—
ps
1.875 to 20 MHz Integration Bandwidth
CMOS 3.3 V²
—
0.5
—
ps
Notes:
1. 50 to 810 MHz, 3.3 V/2.5 V only.
2. 50 to 160 MHz, single-ended CMOS output phase jitter measured using 33  series termination into 50  phase noise
test equipment. 3.3 V supply voltage option only.
Table 6. CLK± Output Phase Jitter (Si599)
(Typical values TA = 25 ºC, V_DD = 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless otherwise
noted)
Parameter
Phase Jitter (RMS)^1,2
for F_OUT of 50 MHz < F_OUT
810 MHz
Symbol
Test Condition
_J Kv = 45 ppm/V
12 kHz to 20 MHz
Kv = 95 ppm/V
12 kHz to 20 MHz
Kv = 125 ppm/V
12 kHz to 20 MHz
Kv = 185 ppm/V
12 kHz to 20 MHz
Kv = 380 ppm/V
12 kHz to 20 MHz
Min
Typ
Max Units
—
0.5
—
ps
—
0.5
—
ps
—
0.5
—
ps
—
0.5
—
ps
—
0.7
—
ps
Notes:
1. Differential Modes: LVPECL/LVDS/CML.
2. For best jitter and phase noise performance, always choose the smallest K_V that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.
8
Rev. 1.0