SI598 Datasheet, PDF (14/28 Pages) Silicon Laboratories – Programmable with 28 parts per trillion frequency resolution

Si598/Si599
3. Unfreeze the DCO and assert the NewFreq bit (bit 6
of Register 135) within the maximum Unfreeze to
NewFreq Timeout in Table 12, “Programming
Constraints and Timing,” on page 10.
The process of freezing and unfreezing the DCO will
cause the output clock to momentarily stop and start at
any arbitrary point during a clock cycle. This process
can take up to 10 ms. Circuitry that is sensitive to
glitches or runt pulses may have to be reset after the
new frequency configuration is written.
Example:
An Si598 generating 156.25 MHz must be re-configured
to generate a 161.1328125 MHz clock (156.25 MHz x
66/64). This frequency change is greater than
±3500 ppm.
f_out = 156.25 MHz
Read the current values for RFREQ, HS_DIV, N1:
RFREQ_current =
34265439877d
0x7FA611E85 = 34265439877d,
/ 2²⁸ = 127.64871074631810d
HS_DIV = 4
N1 = 8
Calculate f_XTAL, f_{DCO_current}
f_{DCO_current} = f_out  HSDV  N1 = 5.000000000 GHz
f_XTAL = _R-----_Ff--^D--_R--^C---_E^O----^__Q--^c---^uc--^r-_u-^r-^e-_r--_rn--_e-^t--_n--_t = 39.17 MHz
Given f_{out_new} = 161.1328125 MHz, choose output
dividers that will keep f_DCO within the range of 4.85 to
5.67 GHz. In this case, keeping the same output
dividers will still keep f_DCO within its range limits:
f_{DCO_new} = f_{out_new}  HSDV_new  N1_new
= 161.1328125 MHz  4  8 = 5.156250000 GHz
Calculate the new value of RFREQ given the new DCO
frequency:
RFREQ_new = ^f--^D---_f-^C-_X--^O-_T---^_A--ⁿ-_L--^e---^w- = 131.637733d= 0x83A342779
3.2. I²C Interface
The control interface to the Si598 is an I²C-compatible
2-wire bus for bidirectional communication. The bus
consists of a bidirectional serial data line (SDA) and a
serial clock input (SCL). Both lines must be connected
to the positive supply via an external pullup.Fast mode
operation is supported for transfer rates up to 400 kbps
as specified in the I²C-Bus Specification standard.
Figure 4 shows the command format for both read and
write access. Data is always sent MSB. Data length is 1
byte. Read and write commands support 1 or more data
bytes as illustrated. The master must send a Not
Acknowledge and a Stop after the last read data byte to
terminate the read command. The timing specifications
and timing diagram for the I²C bus can be found in the
I²C-Bus Specification standard (fast mode operation).
The device I²C address is specified in the part number.
S Slave Address 0 A Byte Address A _Data A Data A _P
Write Command
(Optional 2^nd data byte and acknowledge illustrated)
S Slave Address 0 A Byte Address A _S Slave Address _{1 A} Data A Data N P
Read Command
(Optional data byte and acknowledge before the last data byte and not acknowledge illustrated)
From master to slave
From slave to master
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH).
Required after the last data byte to signal the end of the read comand to the slave.
S – START condition
P – STOP condition
Figure 4. I²C Command Format
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Rev. 1.0