SI53340 Datasheet, PDF (9/23 Pages) Silicon Laboratories – 1:4 LOW-JITTER LVDS CLOCK BUFFER WITH 2:1 INPUT MUX

Si53340
2.2. Input Bias Resistors
Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected.
The noninverting input is biased with a 18.75 k pulldown to GND and a 75 k pullup to V_DD. The inverting input is
biased with a 75 k pullup to V_DD.
Figure 5. Input Bias Resistors
2.3. Input Mux
The Si53340 provides two clock inputs for applications that need to select between one of two clock sources. The
CLK_SEL pin selects the active clock input. The table below summarizes the input and output clock based on the
input mux and output enable pin settings.
Table 12. Input Mux Logic
CLK_SEL CLK0
CLK1
Q¹
Q
L
L
X
L
H
L
H
X
H
L
H
X
L
L
H
H
X
H
H
L
Notes:
1. On the next negative transition of CLK0 or CLK1.
2.4. Output Clock Termination Options
The recommended output clock termination options are shown below. Unused outputs can be left floating. Do not
short unused outputs to ground.
Rev. 1.0
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