SI53340 Datasheet, PDF (1/23 Pages) Silicon Laboratories – 1:4 LOW-JITTER LVDS CLOCK BUFFER WITH 2:1 INPUT MUX

Si53340
1:4 LOW-JITTER LVDS CLOCK BUFFER WITH 2:1 INPUT MUX
Features
 4 LVDS outputs
 V_DD: 1.8 / 2.5 / 3.3 V
 Ultra-low additive jitter: 45 fs rms _{ 16-QFN (3 mm x 3 mm)}
 Wide frequency range: dc to
1250 MHz
 2:1 input mux
 RoHS compliant, Pb-free
 Industrial temperature range:
–40 to +85 °C
 Universal input stage accepts
differential or LVCMOS clock
Applications
 High-speed clock distribution  Storage
 Ethernet switch/router
 Telecom
 Optical Transport Network (OTN)  Industrial
 SONET/SDH
 Servers
 PCI Express Gen 1/2/3
 Backplane clock distribution
Description
The Si53340 is an ultra low jitter four output LVDS buffer. The Si53340
features a 2:1 input mux, making it ideal for redundant clocking
applications. Utilizing Silicon Laboratories’ advanced fan-out clock
technology, the Si53340 guarantees low additive jitter, low skew, and low
propagation delay variability from dc to 1250 MHz.
The Si53340 features minimal cross-talk and excellent supply noise
rejection, simplifying low jitter clock distribution in noisy environments.
Functional Block Diagram
Ordering Information:
See page 19.
Pin Assignments
Patents pending
Rev. 1.0 7/15
Copyright © 2015 by Silicon Laboratories
Si53340