SI53340 Datasheet, PDF (12/23 Pages) Silicon Laboratories – 1:4 LOW-JITTER LVDS CLOCK BUFFER WITH 2:1 INPUT MUX

Si53340
2.6. Typical Phase Noise Performance
Each of the following three figures shows three phase noise plots superimposed on the same diagram.
Source Jitter: Reference clock phase noise.
Total Jitter (SE): Combined source and clock buffer phase noise measured as a single-ended output to the phase
noise analyzer and integrated from 12 kHz to 20 MHz.
Total Jitter (Diff'l): Combined source and clock buffer phase noise measured as a differential output to the phase
noise analyzer and integrated from 12 kHz to 20 MHz. The differential measurement as shown in each figure is
made using a balun. See Figure 1 on page 6.
Note: To calculate the total RMS phase jitter when adding a buffer to your clock tree, use root-sum-square (RSS) addition.
The total jitter is a measure of the source plus the buffer's additive phase jitter. The additive jitter (rms) of the buffer
can then be calculated (via root-sum-square addition).
Figure 8. Source, Additive, and Total Jitter (156.25 MHz)
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Rev. 1.0