SI53340 Datasheet, PDF (5/23 Pages) Silicon Laboratories – 1:4 LOW-JITTER LVDS CLOCK BUFFER WITH 2:1 INPUT MUX

Si53340
Table 6. Additive Jitter, Differential Clock Input
V_DD
Input^1,2
Output
Additive Jitter
(fs rms, 12 kHz to
20 MHz)³
Freq Clock Format Amplitude
Differential Clock Format Typ
Max
(MHz)
V_IN
20%-80% Slew
(Single-Ended, ^{Rate (V/ns)}
Peak-to-Peak)
3.3
725
Differential
0.15
0.637
LVDS
50
65
3.3 156.25 Differential
0.5
2.5
725
Differential
0.15
0.458
0.637
LVDS
LVDS
150
200
50
65
2.5 156.25 Differential
0.5
0.458
LVDS
145
195
Notes:
1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock
Buffer’s Additive Jitter Performance” for more information.
2. AC-coupled differential inputs.
3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1.
Table 7. Additive Jitter, Single-Ended Clock Input
V_DD
Input^1,2
Output
Additive Jitter
(fs rms, 12 kHz to
20 MHz)³
Freq Clock Format Amplitude SE 20%-80% Clock Format
Typ
Max
(MHz)
V_IN
(single-ended,
Slew Rate
(V/ns)
peak to peak)
3.3 156.25 Single-ended
2.18
1
LVDS
150
200
2.5 156.25 Single-ended
2.18
1
LVDS
145
195
Notes:
1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock
Buffer’s Additive Jitter Performance” for more information.
2. DC-coupled single-ended inputs.
3. Measured differentially using a balun at the phase noise analyzer input (see Figure 1).
Figure 1. Differential Measurement Method Using a Balun
Rev. 1.0
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