SI53340 Datasheet, PDF (22/23 Pages) Silicon Laboratories – 1:4 LOW-JITTER LVDS CLOCK BUFFER WITH 2:1 INPUT MUX

DOCUMENT CHANGE LIST
Revision 0.9 to 1.0
 Update operating conditions, including LVCMOS and
HCSL voltage support.
 Removed voltage reference feature.
 Updated Table 2, “Input Clock Specifications,” on
page 4.
 Updated Table 3, “DC Common Characteristics,” on
page 4.
 Updated Table 4, “Output Characteristics—LVDS,”
on page 5.
 Updated Table 10, “LVPECL, LVCMOS, and LVDS
Input Clock Options,” on page 8.
 Updated output voltage specifications.
 Improved data for additive jitter specifications.
 Improved typical phase noise plots.
 Updated input/output termination recommendations.
 Improved performance specifications with more
detail.
 Updated ESD specifications.
Si53340
Rev. 1.0
22