SI53340 Datasheet, PDF (16/23 Pages) Silicon Laboratories – 1:4 LOW-JITTER LVDS CLOCK BUFFER WITH 2:1 INPUT MUX

Si53340
3. Pin Description: 16-Pin QFN
Table 13. Pin Descriptions
Pin
Name Type*
1
GND
GND Ground
Description
2 CLK_SEL I MUX Input Select Pin (LVCMOS)
When CLK_SEL is high, CLK1 is selected
When CLK_SEL is low, CLK0 is selected
CLK_SEL contains an internal pull-down resistor
3
CLK1
I Input Clock 1
4
CLK1
I Input Clock 1 (Complement)
5
V_DD
P Core Voltage Supply.
Bypass with 1.0 μF capacitor and place as close to the VDD pin as possible.
6
CLK0
I Input Clock 0
7
CLK0
I Input Clock 0 (Complement)
8
NC
— No connect. Leave this pin unconnected.
9
Q0
O Output Clock 0
10
Q0
O Output Clock 0 (complement)
11
Q1
O Output Clock 1
16
Rev. 1.0