SI53340 Datasheet, PDF (4/23 Pages) Silicon Laboratories – 1:4 LOW-JITTER LVDS CLOCK BUFFER WITH 2:1 INPUT MUX

Si53340
Table 4. Output Characteristics—LVDS
(V_DD = 1.8 V 5%, 2.5 V  5%, or 3.3 V 10%,T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Single-Ended Output V_SE
R_L = 100 Ω across Q_N and Q_N
200
Swing
—
490
mV
Output Common
V_COM1
V_DD = 2.38 to 2.63 V, 2.97 to
1.10
1.25
1.35
V
Mode Voltage
3.63 V, R_L = 100 Ω across Q_N
(V_DD = 2.5 V or 3.3V)
and Q_N
Output Common
V_COM2 V_DD = 1.71 to 1.89 V, R_L = 100 Ω
0.85
0.97
1.25
V
Mode Voltage
across Q_N
(V_DD = 1.8 V)
and Q_N
Table 5. AC Characteristics
(V_DD = 1.8 V 5%, 2.5 V  5%, or 3.3 V 10%,T_A = –40 to 85 °C)
Parameter
Symbol
Frequency
F
Duty Cycle
D_C
Note: 50% input duty cycle.
Minimum Input Clock
SR
Slew Rate
Output Rise/Fall Time
Minimum Input Pulse
Width
Additive Jitter
(Differential Clock Input)
T_R/T_F
T_W
J
Test Condition
20/80% T_R/T_F<10% of period
Required to meet prop delay and
additive jitter specifications
(20–80%)
V_DD = 2.5 / 3.3 V, F = 725 MHz,
0.75 V/ns input slew rate
Min
dc
47
0.75
—
360
—
Typ Max Unit
—
1250 MHz
50
53
%
—
—
V/ns
—
325
ps
—
—
ps
50
65
fs
Propagation Delay
Output to Output Skew¹
Part to Part Skew²
Power Supply Noise
Rejection³
T_PLH,
T_PHL
T_SK
T_PS
PSRR
10 kHz sinusoidal noise
100 kHz sinusoidal noise
650
850 1050 ns
—
—
50
ps
—
—
125
ps
—
–70
—
dBc
—
–65
—
dBc
500 kHz sinusoidal noise
—
–60
—
dBc
1 MHz sinusoidal noise
—
–57.5
—
dBc
Notes:
1. Output to output skew specified for outputs with an identical configuration.
2. Defined as skew between any output on different devices operating at the same supply voltages, temperatures, and
equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross
points.
3. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to V_DD (3.3 V = 100 mV_PP) and noise spur
amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details.
4
Rev. 1.0