SI53340 Datasheet, PDF (20/23 Pages) Silicon Laboratories – 1:4 LOW-JITTER LVDS CLOCK BUFFER WITH 2:1 INPUT MUX

Si53340
6. PCB Land Pattern
Figure 13 shows the PCB land pattern dimensions for the 3x3 mm 16-pin QFN package. Table 15 lists the values
for the dimensions shown in the illustration.
Figure 13. Si53340 3x3 mm 16-QFN Package Land Pattern
Table 15. PCB Land Pattern Dimensions
Dimension
mm
C1
3.00
C2
3.00
E
0.50
X1
0.30
Y1
0.80
X2
1.75
Y2
1.75
Notes:
General
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is
calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 μm minimum, all the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
8. A 2x2 array of 0.65 mm square openings on a 0.90 mm pitch should be used for the center ground pad.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
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Rev. 1.0