SI53365 Datasheet, PDF (8/14 Pages) Silicon Laboratories – 1:8 LOW JITTER CMOS CLOCK BUFFER

Si53365
3. Pin Description: 16-Pin TSSOP
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
CLK
OE
Q0
GND
V_DD
Q4
GND
Q6
Q7
V_DD
Q5
GND
Q2
V_DD
Q3
Q1
CLK ¹
OE ²
Q0 3
GND 4
VDD 5
Q4 6
GND 7
Q6 ⁸
16 Q1
15 Q3
14 VDD
13 Q2
12 GND
11 _Q5
10 VDD
9 _Q7
Table 9. Si53365 Pin Description
Description
Input clock.
Output enable.
When OE=high, the clock outputs are enabled.
When OE=low, the clock outputs are low.
OE contains an internal pull-up resistor.
Output clock 0.
Ground.
Core voltage supply.
Bypass with 1.0 μF capacitor and place as close to the V_DD pin as possible.
Output clock 4.
Ground.
Output clock 6.
Output clock 7.
Core voltage supply.
Bypass with 1.0 μF capacitor and place as close to the V_DD pin as possible.
Output clock 5.
Ground.
Output clock 2.
Core voltage supply.
Bypass with 1.0 μF capacitor and place as close to the V_DD pin as possible.
Output clock 3.
Output clock 1.
8
Rev. 1.0