SI53365 Datasheet, PDF (6/14 Pages) Silicon Laboratories – 1:8 LOW JITTER CMOS CLOCK BUFFER

Si53365
2. Functional Description
The Si53365 is a low jitter, low skew 1:8 CMOS buffer with asynchronous output enable. The Si53365 is ideal for
low jitter LVCMOS clock distribution.
2.1. Input Termination
Figure 1 shows the recommended input clock termination.
V_{DDO = 3.3V, 2.5V, 1.8V}
CMOS
Rs
Driver
50
CLK
V_DD
Si533xx
Note: V_DDO and V_DD must be at the same voltage level.
Figure 1. LVCMOS DC-Coupled Input Termination
2.2. Output Enable Logic
The table below summarizes the input and output clock state based on the output enable pin setting.
Table 8. Output Logic
INPUTS
CLK
OE
X
L
OUTPUTS
Qn
L
L
H
L
H
H
H
2.3. Output Clock Termination Options
The recommended output clock termination options are shown below. Unused output clocks should be left floating.
Si533xx
CMOS Driver
Zout
Rs
Zo
50
CMOS
Receivers
C_L = 15 pF
Figure 2. LVCMOS Output Termination
6
Rev. 1.0