SI53365 Datasheet, PDF (10/14 Pages) Silicon Laboratories – 1:8 LOW JITTER CMOS CLOCK BUFFER

Si53365
5. Package Outline
5.1. 16-TSSOP Package Diagram
Figure 4. Si53365 16-TSSOP Package Diagram
Table 10. Package Dimensions
Dimension
Min
A
—
A1
0.05
A2
0.80
Nom
Max
—
1.20
—
0.15
1.00
1.05
Dimension Min
e
L
0.45
L2
Nom
Max
0.65 BSC
0.60
0.75
0.25 BSC
b
0.19
—
0.30
θ
0°
—
8°
c
0.09
—
0.20
aaa
0.10
D
4.90
5.00
5.10
bbb
0.10
E
6.40 BSC
ccc
0.20
E1
4.30
4.40
4.50
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-153, Variation AB.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
10
Rev. 1.0