SI53365 Datasheet, PDF (4/14 Pages) Silicon Laboratories – 1:8 LOW JITTER CMOS CLOCK BUFFER

Si53365
Table 5. AC Characteristics
(V_DD = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%,T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Frequency
F
LVCMOS
dc
Duty Cycle
Note: 50% input duty
cycle.
Minimum Input Clock
Slew Rate
D_C 200 MHz, 50 Ω to VDD/2, 20/80%
40
T_R/T_F<10% of period
SR Required to meet prop delay and 0.75
additive jitter specifications
(20–80%)
Output Rise/Fall Time T_R/T_F
200 MHz, 50 Ω, 20/80%,
—
2 pF load, 12 mA drive strength
Minimum Input Pulse
T_W
2
Width
Additive Jitter
J
3.3 V, 200 MHz,
—
(12 kHz – 20 MHz)
Vin = 1.7 V_PP @ 1 V/ns
3.3 V, 156.25 MHz,
—
Vin = 2.18 V_PP @ 1 V/ns
2.5 V, 200 MHz,
—
Vin = 1.7 V_PP @ 1 V/ns
2.5 V, 156.25 MHz,
—
Vin = 2.18 V_PP @ 1 V/ns
Propagation Delay
T_PLH,
Low-to-high, high-to-low
1.5
T_PHL
Single-ended, C_L = 2 pF
Output Enable Time
T_EN
F = 1 MHz
—
F = 100 MHz
—
Output Disable Time
T_DIS
F = 1 MHz
—
F = 100 MHz
—
Part to Part Skew
T_SKPP
C_L = 2 pF
0
Output to Output
T_SK
C_L = 2 pF
—
Skew
Typ
Max
Unit
—
200
MHz
50
60
%
—
—
V/ns
—
850
ps
—
—
ns
130
180 fs-rms
125
220 fs-rms
115
250 fs-rms
125
240 fs-rms
3.0
4.5
ns
10
—
ns
10
—
ns
20
—
ns
20
—
ns
—
300
ps
40
125
ps
4
Rev. 1.0