SI53365 Datasheet, PDF (11/14 Pages) Silicon Laboratories – 1:8 LOW JITTER CMOS CLOCK BUFFER

6. PCB Land Pattern
6.1. 16-TSSOP Package Land Pattern
Si53365
Figure 5. Si53365 16-TSSOP Package Land Pattern
Table 11. PCB Land Pattern
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.80
E
Pad Row Pitch
0.65
X1
Pad Width
0.45
Y1
Pad Length
1.40
Notes:
1. This Land Pattern Design is based on the IPC-7351
guidelines.
2. All feature sizes shown are at Maximum Material
Condition (MMC) and a card fabrication tolerance of
0.05 mm is assumed.
Rev. 1.0
11