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SI53302 Datasheet, PDF (8/34 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX | |||
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Si53302
Table 10. AC Characteristics (Continued)
(VDD = VDDOX = 1.8 V ï±ï 5%, 2.5 V ï± 5%, or 3.3 V ï±ï 10%,TA = â40 to 85 °C)
Parameter
Power Supply Noise
Rejection5
Symbol
PSRR
Test Condition
10 kHz sinusoidal noise
100 kHz sinusoidal noise
500 kHz sinusoidal noise
Min Typ Max Unit
â
â63
â
dBc
â
â62
â
dBc
â
â58
â
dBc
1 MHz sinusoidal noise
â
â55
â
dBc
Notes:
1. When using the on-chip clock divider, a minimum input clock slew rate of 30 mV/ns is required.
2. HCSL measurements were made with receiver termination. See Figure 9 on page 19.
3. Output to Output skew specified for outputs with an identical configuration.
4. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and
equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross
points.
5. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDDOX (3.3 V = 100 mVPP) and noise spur
amplitude measured. See âAN491: Power Supply Rejection for Low-Jitter Clocksâ for further details.
8
Rev. 1.1
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