SI53302 Datasheet, PDF (33/34 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

DOCUMENT CHANGE LIST
Revision 0.41 to 1.0
 Added Loss of Signal (LOS) feature with description
and pin assignments.
 Update operating conditions, including LVCMOS and
HCSL voltage support.
 Updated Table 2, “Input Clock Specifications,” on
page 3.
 Updated Table 3, “DC Common Characteristics,” on
page 5.
 Updated Table 4, “Output Characteristics
(LVPECL),” on page 6.
 Updated Table 10, “AC Characteristics,” on page 7.
 Updated output voltage specifications
 Improved data for additive jitter specifications.
 Improved typical phase noise plots.
 Updated input/output termination recommendations.
Revision 1.0 to Revision 1.1
 Corrected front-page buffer block diagram.
 Improved performance specifications with more
detail.
Added additional information to clarify the use of the
voltage reference feature.
Added pin type description to Table 21, “Si53302 44-
Pin QFN Descriptions,” on page 26.
Added low-voltage termination options for 1.2 V and
1.5 V LVCMOS support.
Clarified output clock bank A and bank B
assignments.
Si53302
Rev. 1.1
33