SI53302 Datasheet, PDF (27/34 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53302
Pin #
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Table 21. Si53302 44-Pin QFN Descriptions (Continued)
Name
NC
Type*
— No connect
Description
VDD
LOS0
CLK0
P Core voltage supply
Bypass with 1.0 µF capacitor and place close to the VDD pin as possible
O The LOS0 status pin indicates whether a clock is present (LOS0 = 0) or not
present
(LOS0 = 1) at the CLK0 input.
I Input clock 0
CLK0
OEA
V_REF
OEB
CLK1
I Input clock 0 (complement)
When CLK0 is driven by a single-ended input, connect CLK0 to VDD/2.
I Output enable—Bank A
When OE = high, the Bank A outputs are enabled
When OE = low, Q is held low and Q is held high for differential formats
For LVCMOS, both Q and Q are held low when OE is set low
OEA contains an internal pull-up resistor
O Input clock reference voltage used to bias CLK0 or CLK1 clock input pins.
V_REF is required when a differential input clock is applied to the device and
terminated as a single-ended reference. V_REF may be left unconnected for
LVCMOS or differential clock inputs. See “2.3. Input Clock Voltage Refer-
ence (VREF)” for details.
I Output enable—Bank B
When OE = high, the Bank B outputs are enabled
When OE = low, Q is held low and Q is held high for differential formats
For LVCMOS, both Q and Q are held low when OE is set low
OEB contains an internal pull-up resistor.
I Input clock 1
CLK1
LOS1
GND
I Input clock 1 (complement)
When CLK1 is driven by a single-ended input, connect CLK1 to VDD/2.
O The LOS1 status pin indicates whether a clock is present (LOS1 = 0) or not
present
(LOS1 = 1) at the CLK1 input.
GND Ground
CLK_SEL
Q9
I MUX input select pin (LVCMOS)
Clock inputs are switched without the introduction of glitches
When CLK_SEL is high, CLK1 is selected
When CLK_SEL is low, CLK0 is selected
CLK_SEL contains an internal pull-down resistor
O Output clock 9 (complement)
Q9
O Output clock 9
Q8
O Output clock 8 (complement)
Rev. 1.1
27