SI53302 Datasheet, PDF(1/34 Page) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

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SI53302 Datasheet, PDF (1/34 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53302

1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL

TRANSLATOR WITH 2:1 INPUT MUX

Features

ï® 10 differential or 20 LVCMOS outputsï® Independent VDD and VDDO:

ï® Ultra-low additive jitter: 45 fs rms

1.8/2.5/3.3 V

ï® Wide frequency range: 1 to 725 MHz ï® 1.2/1.5 V LVCMOS output support

ï® Any-format input with pin selectable ï® Excellent power supply noise

output formats: LVPECL, Low Power rejection (PSRR)

LVPECL, LVDS, CML, HCSL,

LVCMOS

ï® Selectable LVCMOS drive strength to

tailor jitter and EMI performance

ï® 2:1 clock input mux

ï® Glitchless input clock switching

ï® Loss of signal (LOS) monitors for

loss of input clock

ï® Synchronous output enable

ï® Small size: 44-QFN (7 mm x 7 mm)

ï® Output clock division: /1, /2, /4

ï® RoHS compliant, Pb-free

ï® Industrial temperature range:

â40 to +85 Â°C

Ordering Information:

See page 29.

Applications

ï® High-speed clock distribution

ï® Ethernet switch/router

ï® Optical Transport Network (OTN)

ï® SONET/SDH

ï® PCI Express Gen 1/2/3

ï® Storage

ï® Telecom

ï® Industrial

ï® Servers

ï® Backplane clock distribution

Description

The Si53302 is an ultra low jitter ten output differential buffer with pin-selectable

output clock signal format and divider selection. The Si53302 features a 2:1 mux

with glitchless switching, making it ideal for redundant clocking applications. The

Si53302 utilizes Silicon Laboratories' advanced CMOS technology to fanout

clocks from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low

propagation delay variability. The Si53302 features minimal cross-talk and

provides superior supply noise rejection, simplifying low jitter clock distribution in

noisy environments. Independent core and output bank supply pins provide

integrated level translation without the need for external circuitry.

Pin Assignments

Si53302

DIVA 1

SFOUTA[1] 2

SFOUTA[0] 3

Q2 4

Q2 5

GND 6

Q1 7

Q1 8

Q0 9

Q0 10

NC 11

GND

PAD

33 DIVB

32 SFOUTB[1]

31 SFOUTB[0]

30 Q7

29 Q7

28 NC

27 Q8

26 Q8

25 Q9

24 Q9

23 CLK_SEL

Patents pending

Functional Block Diagram

Vref

LOS0

LOS1

CLK0

CLK1

CLK_SEL

Vref

Generator

LOS

Monitor

VDD

Power

Supply

Filtering

DivA

Bank A

Switching

Logic

DivB

Bank B

DIVA

VDDOA

SFOUTA[1:0]

OEA

Q0, Q1, Q2, Q3, Q4

/Q0, /Q1, /Q2, /Q3, /Q4

DIVB

VDDOB

SFOUTB[1:0]

OEB

Q5, Q6, Q7, Q8, Q9

/Q5, /Q6, /Q7, /Q8, /Q9

Rev. 1.1 9/14

Si53302

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