SI53302 Datasheet, PDF(4/34 Page) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

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SI53302 Datasheet, PDF (4/34 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

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Si53302

Table 3. DC Common Characteristics

(VDD = 1.8 V ï±ï 5%, 2.5 V ï± 5%, or 3.3 V ï±ï 10%,TA = â40 to 85 Â°C)

Parameter

Supply Current

Output Buffer

Supply Current

(Per Clock Output)

@100 MHz (diff)

@200 MHz (CMOS)

Symbol

IDD

IDDOX

Test Condition

LVPECL (3.3 V)

Low Power LVPECL (3.3 V)*

LVDS (3.3 V)

CML (3.3 V)

Min

Typ

Max

100

HCSL, 100 MHz, 2 pF load (3.3 V)

CMOS (1.8 V, SFOUT = Open/0),

per output, CL = 5 pF, 200 MHz

CMOS (2.5 V, SFOUT = Open/0),

per output, CL = 5 pF, 200 MHz

CMOS (3.3 V, SFOUT = 0/1),

per output, CL = 5 pF, 200 MHz

Input Clock Voltage

Reference

VREF

VREF pin

IREF = +/-500 ïA

VDD/2

Input High Voltage

VIH

SFOUTx, DIVx

CLK_SEL, OEx

0.8 x

VDD

Input Mid Voltage

VIM

SFOUTx, DIVx

3-level input pins

0.45 x

VDD

0.5 x

VDD

0.55 x

VDD

Input Low Voltage

VIL

SFOUTx, DIVx

CLK_SEL, OEx

0.2 x

VDD

Output Voltage High

VOH

(LOSx)

IDD = â1 mA

0.8xVDD â

Output Voltage Low

VOL

(LOSx)

IDD = 1 mA

â 0.2xVDD

Internal Pull-down

Resistor

RDOWN

CLK_SEL, DIVx, SFOUTx

Internal Pull-up

RUP

Resistor

OEx, DIVx, SFOUTx

*Note: Low-power LVPECL mode supports an output termination scheme that will reduce overall system power.

Unit

kï

Rev. 1.1

▷