SI53302 Datasheet, PDF (7/34 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53302
Table 10. AC Characteristics (Continued)
(V_DD = V_DDOX = 1.8 V 5%, 2.5 V  5%, or 3.3 V 10%,T_A = –40 to 85 °C)
Parameter
Minimum Input Clock
Slew Rate¹
Symbol
Test Condition
Min Typ Max Unit
SR
Required to meet prop delay and 0.75
—
additive jitter specifications
(20–80%)
—
V/ns
Output Rise/Fall Time
T_R/T_F
LVDS, 20/80%
LVPECL, 20/80%
HCSL², 20/80%
—
—
325
ps
—
—
350
ps
—
—
280
ps
CML, 20/80%
—
—
350
ps
Low-Power LVPECL, 20/80%
—
—
325
ps
LVCMOS 200 MHz, 20/80%,
2 pF load
—
—
750
ps
Minimum Input Pulse
Width
Propagation Delay
T_W
500
—
—
ps
T_PLH, LVCMOS (12mA drive with no load) 1250 2000 2750
ps
T_PHL
LVPECL
600
800 1000
ps
LVDS
600
800 1000
ps
Output Enable Time
T_EN
F = 1 MHz
F = 100 MHz
—
2500
—
ns
—
30
—
ns
F = 725 MHz
—
5
—
ns
Output Disable Time
T_DIS
F = 1 MHz
F = 100 MHz
—
2000
—
ns
—
30
—
ns
Output to Output Skew³
F = 725 MHz
—
T_SK
LVCMOS (12 mA drive to no load)
—
LVPECL
—
5
—
ns
50
120
ps
35
70
ps
LVDS
—
35
70
ps
Part to Part Skew⁴
T_PS
Differential
—
—
150
ps
Notes:
1. When using the on-chip clock divider, a minimum input clock slew rate of 30 mV/ns is required.
2. HCSL measurements were made with receiver termination. See Figure 9 on page 19.
3. Output to Output skew specified for outputs with an identical configuration.
4. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and
equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross
points.
5. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to V_DDOX (3.3 V = 100 mV_PP) and noise spur
amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details.
Rev. 1.1
7