SI53302 Datasheet, PDF (28/34 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53302
Table 21. Si53302 44-Pin QFN Descriptions (Continued)
Pin #
27
Name
Q8
Type*
O Output clock 8
Description
28
NC
— No connect
29
Q7
O Output clock 7 (complement)
30
Q7
O Output clock 7
31
SFOUTB[0]
32
SFOUTB[1]
33
DIVB
34
V_DDOB
35
Q6
I Output signal format control pin for Bank B
Three-level input control. Internally biased at VDD/2. Can be left floating or
tied to ground or V_DD.
I Output signal format control pin for Bank B
Three-level input control. Internally biased at VDD/2. Can be left floating or
tied to ground or V_DD.
I Output divider configuration bit for Bank B
Three-level input control. Internally biased at VDD/2. Can be left floating or
tied to ground or V_DD.
P Output Clock Voltage Supply—Bank B (Outputs: Q5 to Q9)
Bypass with 1.0 µF capacitor and place close to the V_DDOB pin as possible
O Output clock 6 (complement)
36
Q6
O Output clock 6
37
Q5
O Output clock 5 (complement)
38
Q5
O Output clock 5
39
GND
GND Ground
40
Q4
O Output clock 4 (complement)
41
Q4
O Output clock 4
42
Q3
O Output clock 3 (complement)
43
Q3
O Output clock 3
44
GND
Pad
V_DDOA
GND
P
GND
Output Voltage Supply—Bank A (Outputs: Q0 to Q4)
Bypass with 1.0 µF capacitor and place close to the V_DDOA pin as possible
Ground Pad
Power supply ground and thermal relief
*Pin types are: I = input, O = output, P = power, GND = ground.
28
Rev. 1.1