SI53302 Datasheet, PDF (26/34 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

Si53302
3. Pin Description: 44-Pin QFN
DIVA ¹
SFOUTA[1] ²
SFOUTA[0] ³
Q2 ⁴
Q2 ⁵
GND ⁶
Q1 ⁷
Q1 ⁸
Q0 ⁹
Q0 ¹⁰
NC ¹¹
GND
PAD
33 _DIVB
32 _SFOUTB[1]
31 _SFOUTB[0]
30 _Q7
29 _Q7
28 _NC
27 _Q8
26 _Q8
25 _Q9
24 _Q9
23 _{CLK_SEL}
Pin #
1
2
3
4
5
6
7
8
9
10
Name
DIVA
SFOUTA[1]
SFOUTA[0]
Q2
Q2
GND
Q1
Q1
Q0
Q0
Table 21. Si53302 44-Pin QFN Descriptions
Type*
Description
I Output divider control pin for Bank A
Three-level input control. Internally biased at VDD/2. Can be left floating or
tied to ground or V_DD.
I Output signal format control pin for Bank A
Three-level input control. Internally biased at VDD/2. Can be left floating or
tied to ground or V_DD.
I Output signal format control pin for Bank A
Three-level input control. Internally biased at VDD/2. Can be left floating or
tied to ground or V_DD.
O Output clock 2 (complement)
O Output clock 2
GND Ground
O Output clock 1 (complement)
O Output clock 1
O Output clock 0 (complement)
O Output clock 0
26
Rev. 1.1