SI5020 Datasheet, PDF (8/24 Pages) List of Unclassifed Manufacturers – SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC

Si5020
Table 4. AC Characteristics (PLL Characteristics) (Continued)
(V_A 2.5 V ±5%, T_A = –40 to 85 °C)
Parameter
Jitter Transfer Bandwidth^*
Symbol
J_BW
Test Condition
OC-48 Mode
OC-12 Mode
Min Typ Max
—
—
2.0
—
—
500
Jitter Transfer Peaking^*
Acquisition Time
OC-3 Mode
—
—
130
J_P
—
0.03
0.1
T_AQ
After falling edge of
1.45
1.5
1.7
PWRDN/CAL
From the return of valid
40
60
150
data
Input Reference Clock Duty Cycle
Reference Clock Range
C_DUTY
40
50
60
19.44 — 168.75
Input Reference Clock Frequency
Tolerance
C_TOL
–100
—
100
Frequency Difference at which
LOL
Receive PLL goes out of Lock
(REFCLK compared to the divided
down VCO clock)
450
600
750
Frequency Difference at which
Receive PLL goes into Lock (REF-
CLK compared to the divided
down VCO clock)
LOCK
150
300
450
*Note: Bellcore specifications: GR-253-CORE, Issue 3, September 2000. Using PRBS 2²³ – 1 data pattern.
Unit
MHz
kHz
kHz
dB
ms
s
%
MHz
ppm
ppm
ppm
8
Rev. 1.6