SI5020 Datasheet, PDF (11/24 Pages) List of Unclassifed Manufacturers – SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC

Si5020
4. Functional Description
The Si5020 utilizes a phase-locked loop (PLL) to
recover a clock synchronous to the input data stream.
This clock is used to retime the data, and both the
recovered clock and data are output synchronously via
current mode logic (CML) drivers. Optimal jitter
performance is obtained by using Silicon Laboratories'
DSPLL technology to eliminate the noise entry points
caused by external PLL loop filter components.
4.1. DSPLL^™
The PLL structure (shown in Figure 1 on page 5) utilizes
Silicon Laboratories' DSPLL technology to eliminate the
need for external loop filter components found in
traditional PLL implementations. This is achieved by
using a digital signal processing (DSP) algorithm to
replace the loop filter commonly found in analog PLL
designs. This algorithm processes the phase detector
error term and generates a digital control value to adjust
the frequency of the voltage-controlled oscillator (VCO).
Because external loop filter components are not
required, sensitive noise entry points are eliminated,
making the DSPLL less susceptible to board-level noise
sources that make SONET/SDH jitter compliance
difficult to attain.
4.2. PLL Self-Calibration
The Si5020 achieves optimal jitter performance by
using self-calibration circuitry to set the loop gain
parameters within the DSPLL. For the self-calibration
circuitry to operate correctly, the power supply voltage
must exceed 2.25 V when calibration occurs. For best
performance, the user should force a self-calibration
once the supply has stabilized on powerup.
A self-calibration can be initiated by forcing a high-to-
low transition on the powerdown control input, PWRDN/
CAL, while a valid reference clock is supplied to the
REFCLK input. The PWRDN/CAL input should be held
high at least 1 s before transitioning low to guarantee a
self-calibration. Several application circuits that could be
used to initiate a power-on self-calibration are provided
in Silicon Laboratories’ “AN42: Controlling DSPLL™
Self-Calibration for the Si5020/5018/5010 CDR Devices
and Si531x Clock Multiplier/Regenerator Devices.”
Multi-rate operation is achieved by configuring the
device to divide down the output of the VCO to the
desired data rate. The divide factor is configured by the
RATESEL0-1 pins. The RATESEL0-1 configuration and
associated data rates are given in Table 7.
Table 7. Multi-Rate Configuration
RATESEL
[0:1]
SONET/
SDH
Gigabit
Ethernet
OC-48
with
15/14
FEC
CLK
Divider
00
2.488 Gbps
—
2.67 Gbps 1
10
1.244 Gbps 1.25 Gbps
—
2
01
622.08 Mbps
—
—
4
11
155.52 Mbps
—
—
16
4.4. Reference Clock Detect
The Si5020 CDR requires an external reference clock
applied to the REFCLK input for normal device
operation. When REFCLK is absent, the LOL alarm will
always be asserted when it has been determined that
no activity exists on REFCLK, indicating the frequency
lock status of the PLL is unknown. Additionally, the
Si5020 uses the reference clock to center the VCO
output frequency so that clock and data can be
recovered from the input data stream. The device self
configures for operation with one of three reference
clock frequencies. This eliminates the need to externally
configure the device to operate with a particular
reference clock.
The reference clock centers the VCO for a nominal
output of between 2.5 GHz and 2.7 GHz. The VCO
frequency is centered at 16, 32, or 128 times the
reference clock frequency. Detection circuitry
continuously monitors the reference clock input to
determine whether the device should be configured for
a reference clock that is 1/16, 1/32, or 1/128 the
nominal VCO output. Approximate reference clock
frequencies for some target applications are given in
Table 8.
Table 8. Typical REFCLK Frequencies
4.3. Multi-Rate Operation
The Si5020 supports clock and data recovery for OC-48
and STM-16 data streams. In addition, the PLL was
designed to operate at data rates up to 2.7 Gbps to
support OC-48/STM-16 applications that employ
forward error correction (FEC).
SONET/SDH
Gigabit
Ethernet
19.44 MHz
77.76 MHz
155.52 MHz
19.53 MHz
78.125 MHz
156.25 MHz
SONET/
SDH with
15/14 FEC
20.83 MHz
83.31 MHz
166.63 MHz
Ratio of
VCO to
REFCLK
128
32
16
Rev. 1.6
11