SI5020 Datasheet, PDF (17/24 Pages) List of Unclassifed Manufacturers – SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC

Si5020
Pin #
15
16
17
19
20
2, 7, 11, 14
3, 8, 18, and
GND Pad
Table 9. Si5020 Pin Descriptions (Continued)
Pin Name
PWRDN/CAL
CLKOUT–
CLKOUT+
RATESEL0
RATESEL1
VDD
GND
I/O Signal Level
Description
I
LVTTL Powerdown.
To shut down the high-speed outputs and reduce
power consumption, hold this pin high. For normal
operation, hold this pin low.
Calibration.
To initiate an internal self-calibration, force a high-
to-low transition on this pin. (See "PLL Self-Calibra-
tion" on page 11.)
Note: This input has a weak internal pulldown.
O
CML
Differential Clock Output.
The output clock is recovered from the data signal
present on DIN. In the absence of data, the output
clock is derived from REFCLK.
I
LVTTL
Data Rate Select.
These pins configure the onboard PLL for clock and
data recovery at one of four user selectable data
rates. See Table 7 for configuration settings.
Note: These inputs have weak internal pulldowns.
2.5 V
Supply Voltage.
Nominally 2.5 V.
GND
Supply Ground.
Nominally 0.0 V. The GND pad found on the bottom
of the 20-pin micro leaded package (see Figure 12)
must be connected directly to supply ground.
Rev. 1.6
17