SI5020 Datasheet, PDF (12/24 Pages) List of Unclassifed Manufacturers – SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC

Si5020
4.5. Forward Error Correction (FEC)
The Si5020 supports FEC in SONET OC-48 (SDH
STM-16) applications for data rates up to 2.7 Gbps. In
FEC applications, the appropriate reference clock
frequency is determined by dividing the input data rate
by 16, 32, or 128. For example, if an FEC code is used
that produces a 2.70 Gbps data rate, the required
reference clock would be 168.75, 84.375, or 21.09 MHz.
4.6. Lock Detect
The Si5020 provides lock-detect circuitry that indicates
whether the PLL has achieved frequency lock with the
incoming data. The circuit compares the frequency of a
divided-down version of the recovered clock with the
frequency of the applied reference clock (REFCLK). If
the recovered clock frequency deviates from that of the
reference clock by the amount specified in Table 4 on
page 7, the PLL is declared out-of-lock, and the loss-of-
lock (LOL) pin is asserted high. In this state, the PLL will
periodically try to reacquire lock with the incoming data
stream. During reacquisition, the recovered clock may
drift over a ±600 ppm range relative to the applied
reference clock, and the LOL output alarm may toggle
until the PLL has reacquired frequency lock. Due to the
low noise and stability of the DSPLL, under the
condition where data is removed from the inputs, there
is the possibility that the PLL will not drift enough to
render an out-of-lock condition.
If REFCLK is removed, the LOL output alarm will always
be asserted when it has been determined that no
activity exists on REFCLK, indicating the frequency lock
status of the PLL is unknown.
Note: LOL is not asserted during PWRDN/CAL.
4.7. PLL Performance
The PLL implementation used in the Si5020 is fully
compliant with the jitter specifications proposed for
SONET/SDH equipment by Bellcore GR-253-CORE,
Issue 2, December 1995 and ITU-T G.958.
4.7.1. Jitter Tolerance
The Si5020’s tolerance to input jitter exceeds that of the
Bellcore/ITU mask shown in Figure 4. This mask
defines the level of peak-to-peak sinusoid jitter that
must be tolerated when applied to the differential data
input of the device.
Note: There are no entries in the mask table for the data rate
corresponding to OC-24 as that rate is not specified by
either GR-253 or G.958.
Sinusoidal
Input
Jitter (UI p-p)
15
1.5
0.15
Slope = 20 dB/Decade
f0 f1 f2 f3 ft
Frequency
SONET
F0
F1 F2 F3 Ft
Data Rate (Hz) (Hz) (Hz) (kHz) (kHz)
OC- 48
10
600 6000 1000 1000
OC- 12
10
30 300 25 250
OC- 3
10
30 300 6.5 65
Figure 4. Jitter Tolerance Specification
4.7.2. Jitter Transfer
The Si5020 is fully compliant with the relevant Bellcore/
ITU specifications related to SONET/SDH jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a function of jitter frequency (see
Figure 5). These measurements are made with an input
test signal that is degraded with sinusoidal jitter whose
magnitude is defined by the mask in Figure 4.
4.7.3. Jitter Generation
The Si5020 exceeds all relevant specifications for jitter
generation proposed for SONET/SDH equipment. The
jitter generation specification defines the amount of jitter
that may be present on the recovered clock and data
outputs when a jitter free input signal is provided. The
Si5020 typically generates less than 3.0 mUI_rms of jitter
when presented with jitter-free input data.
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Rev. 1.6