SI5020 Datasheet, PDF (15/24 Pages) List of Unclassifed Manufacturers – SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC

Si5020
4.12. Differential Output Circuitry
The Si5020 utilizes a current mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data
(DOUT). An example of output termination with ac coupling is shown in Figure 9. In applications in which direct dc
coupling is possible, the 0.1 F capacitors may be omitted. The differential peak-to-peak voltage swing of the CML
architecture is listed in Table 2 on page 6.
Si5020
V DD
100 
DOUT +,
CLKOUT + ^{0.1  F}
V DD
50 
Zo = 50 
DOUT –,
CLKOUT – ^{0.1  F}
Zo = 50 
100
V DD
50
V DD
Figure 9. Output Termination for DOUT and CLKOUT (AC-coupled)
Rev. 1.6
15