SI5020 Datasheet, PDF (1/24 Pages) List of Unclassifed Manufacturers – SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC

Si5020
SiPHY® MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC
Features
Complete high-speed, low-power, CDR solution includes the following:
 Supports OC-48/12/3, STM-16/4/1,  Exceeds all SONET/SDH jitter
Gigabit Ethernet, and 2.7 Gbps FEC specifications
 Low Power—270 mW (TYP OC-48) Jitter generation
 Small footprint: 4 x 4 mm
2.9 mUI_rms (Typ)
 DSPLL™ eliminates external loop  Device powerdown
filter components
 Loss-of-lock indicator
 3.3 V tolerant control inputs
 Single 2.5 V Supply
Ordering Information:
See page 18.
Applications
 SONET/SDH/ATM routers
 Add/drop multiplexers
 Digital cross connects
 Gigabit Ethernet interfaces
 SONET/SDH test equipment
 Optical transceiver modules
 SONET/SDH regenerators
 Board level serial links
Pin Assignments
Si5020
Description
The Si5020 is a fully-integrated low-power clock and data recovery (CDR)
IC designed for high-speed serial communication systems. It extracts timing
information and data from a serial input at OC-48/12/3, STM-16/4/1, or
Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also
provided for OC-48/STM-16 applications that employ forward error
correction (FEC). DSPLL technology eliminates sensitive noise entry points,
making the PLL less susceptible to board-level interaction and helping to
ensure optimal jitter performance.
The Si5020 represents a new standard in low jitter, low power, and small
size for high-speed CDRs. It operates from a single 2.5 V supply over the
industrial temperature range (–40 to 85 °C).
REXT
VDD
GND
REFCLK+
REFCLK–
20 19 18 17 16
1
15
2
GND
14
3
Pad
13
4 Connection 12
5
11
6 7 8 9 10
Top View
PWRDN
VDD
DOUT+
DOUT–
VDD
Functional Block Diagram
LOL
DIN +
BUF
DIN – 2
D SPL L^TM
Phas e-Locked
Loop
Bias
2
2
R etim er
BUF
2
BUF
2
DOUT +
DOUT –
PW RDN/CAL
CLKOUT +
CLKOUT –
Rev. 1.6 2/15
R EXT
R ATESEL1-0 R EF C LKIN +
REFCLKIN –
Copyright © 2015 by Silicon Laboratories
Si5020