SI5020 Datasheet, PDF (6/24 Pages) List of Unclassifed Manufacturers – SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC

Si5020
Table 2. DC Characteristics
(V_DD = 2.5 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol Test Condition Min
Typ
Max Unit
Supply Current
I_DD
OC-48 and FEC (2.7 GHz)
GbE
OC-12
OC-3
—
108
122
mA
—
113
127
—
117
131
—
124
138
Power Dissipation
P_D
OC-48 and FEC (2.7 GHz)
GbE
OC-12
OC-3
—
270
320 mW
—
283
333
—
293
344
—
310
362
Common Mode Input Voltage
(DIN, REFCLK)*
Single-Ended Input Voltage (DIN, REFCLK)*
Differential Input Voltage Swing
(DIN, REFCLK)*
Input Impedance (DIN, REFCLK)*
Differential Output Voltage Swing (DOUT)
OC48/12/3
V_ICM
V_IS
V_ID
R_IN
V_OD
varies with V_DD
See Figure 1
See Figure 1
Line-to-Line
100  Load
Line-to-Line
— .80 x V_DD —
200
—
750
200
—
1500
84
100
116
780
990
1260
V
mV_PP
mV_PP

mV_PP
Differential Output Voltage Swing (CLKOUT) V_OD
OC48/12/3
100  Load
550
Line-to-Line
900
1260 mV_PP
Output Common Mode Voltage
(DOUT,CLKOUT)
V_OCM
100  Load
—
V_DD –
—
V
Line-to-Line
0.23
Output Impedance (DOUT,CLKOUT)
R_OUT Single-ended
84
100
116

Output Short to GND (DOUT,CLKOUT)
I_SC(–)
—
25
31
mA
Output Short to V_DD (DOUT,CLKOUT)
I_SC(+)
–17.5 –14.5
—
mA
Input Voltage Low (LVTTL Inputs)
V_IL
—
—
.8
V
Input Voltage High (LVTTL Inputs)
V_IH
2.0
—
—
V
Input Low Current (LVTTL Inputs)
I_IL
—
—
10
A
Input High Current (LVTTL Inputs)
I_IH
—
—
10
A
Output Voltage Low (LVTTL Outputs)
V_OL
I_O = 2 mA
—
—
0.4
V
Output Voltage High (LVTTL Outputs)
V_OH
I_O = 2 mA
2.0
—
—
V
Input Impedance (LVTTL Inputs)
R_IN
10
—
—
k
PWRDN/CAL Leakage Current
I_PWRDN V_PWRDN  0.8 V 15
25
35
A
*Note: The DIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage
swing of the signal applied to the active input must exceed the specified minimum Differential Input Voltage Swing (VID
min) and the unused input must be ac coupled to ground. When driving differentially, the difference between the positive
and negative input signals must exceed VID min. (Each individual input signal needs to swing only half of this range.) In
either case, the voltage applied to any individual pin (DIN+, DIN–, REFCLK+, or REFCLK–) must not exceed the
specified maximum Input Voltage Range (VIS max).
6
Rev. 1.6