SI5020 Datasheet, PDF (16/24 Pages) List of Unclassifed Manufacturers – SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC

Si5020
5. Pin Descriptions: Si5020
20 19 18 17 16
REXT 1
VDD 2
GND 3
REFCLK+ 4
REFCLK– 5
GND
Pad
Connection
15 PWRDN
14 VDD
13 DOUT+
12 DOUT–
11 VDD
6 7 8 9 10
Pin #
1
4
5
6
9
10
12
13
Pin Name
REXT
REFCLK+
REFCLK–
LOL
DIN+
DIN–
DOUT–
DOUT+
Figure 10. Si5020 Pin Configuration
Table 9. Si5020 Pin Descriptions
I/O Signal Level
Description
External Bias Resistor.
This resistor is used by onboard circuitry to estab-
lish bias currents within the device. This pin must
be connected to GND through a 10 k1resis-
tor.
I
See Table 2 ^{Differential Reference Clock.}
The reference clock sets the initial operating fre-
quency used by the onboard PLL for clock and data
recovery. Additionally, the reference clock is used to
derive the clock output when no data is present.
O
LVTTL
Loss-of-Lock.
This output is driven high when the recovered clock
frequency deviates from the reference clock by the
amount specified in Table 4 on page 7.
I
See Table 2 ^{Differential Data Input.}
Clock and data are recovered from the differential
signal present on these pins.
O
CML
Differential Data Output.
The data output signal is a retimed version of the
data recovered from the signal present on DIN. It is
phase aligned with CLKOUT and is updated on the
rising edge of CLKOUT.
16
Rev. 1.6