EFM8UB2 Datasheet, PDF (4/50 Pages) Silicon Laboratories – The EFM8UB2 highlighted features are listed below

3. System Overview
3.1 Introduction
EFM8UB2 Data Sheet
System Overview
C2D
C2CK/RSTb
VDD
VREGIN
GND
D+
D-
VBUS
Reset
Power-On
Reset
Supply
Monitor
Power
Net
Voltage
Regulators
Debug / Programming
Hardware
CIP-51 8051 Controller
Core
64/32 KB ISP Flash
Program Memory
256 Byte RAM
4/2 KB XRAM
XTAL1
XTAL2
System Clock Setup
External Oscillator
Internal Oscillator
Clock
Recovery
Low Freq.
Oscillator
USB Peripheral
Full / Low
Speed
Transceiver
Controller
1 KB RAM
Port I/O Configuration
Digital Peripherals
UART0
UART1
Port 0
Drivers
Timers 0, 1,
2, 3, 4, 5
PCA/WDT
Priority
Crossbar
Decoder
Port 1
Drivers
SMBus 0
SMBus 1
SPI
Port 2
Drivers
Crossbar Control
Port 3
SFR
Drivers
Bus
External Memory
Interface
Control
Port 4
P1
Drivers
Address
P2 / P3
P4
Data
Analog Peripherals
VREF
VDD
VREF
+-+-
Comparators
10-bit
500ksps
ADC
VDD
Temp
Sensor
Figure 3.1. Detailed EFM8UB2 Block Diagram
P0.n
P1.n
P2.n
P3.n
P4.n
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.2 | 3