UPIO-M3U1XX Datasheet, PDF (25/28 Pages) Silicon Laboratories – The Unified Development Platform (UDP) provides a development

UPIO-M3U1xx
Table 8. UPIO-M3U1xx Card H4 Pin Descriptions (J4) (Continued)
I/O Card
Pin
36
37
38
39
40
41
42
43
Signal Name
EXTREG_SP_A
I2V_INN_A
I2V_INP_A
GND
HVDA_INN_B
HVDA_INP_B
HVDA_INN_A
HVDA_INP_A
Description
PB3.8 header/External Voltage Regulator SP input
PB0.8 header
PB0.7 header
44
GND
45
CP_NEG_B
46
CP_POS_B
47
CP_NEG_A
48
CP_POS_A
49
CP_OUTA_A
50
CP_OUT_A
51
IDAC_B
52
IDAC_A
53
GND
54
DAC_OUT3
55
DAC_OUT2
56
DAC_OUT1
57
DAC_OUT0
58
DAC_VREFGND
59
DAC_VREF
60
GND
61
ADC_IN3
62
ADC_IN2
63
ADC_IN1
64
ADC_IN0
65
ADC_VREFGND
66
ADC_VREF
67
GND
68
C2D_RX15_A
69
C2D_RX14_A
70
C2D_RX13_A
71
C2D_RX12_A
72
C2D_RX11_A
PB3.5 header/Switch SW3
PB3.4 header/Switch SW2
PB2.14 header
PB2.13 header
PB1.0H header
PB0.15H header
PB0.13 header
PB0.14 header
PB1.11 header
PB1.10 header
PB1.6H header
PB1.5H header
PB0.11 header
PB1.12 header
Rev. 0.1
25