UPIO-M3U1XX Datasheet, PDF (16/28 Pages) Silicon Laboratories – The Unified Development Platform (UDP) provides a development

UPIO-M3U1xx
Table 5. UPIO-M3U1xx Card H1 Pin Descriptions (J1) (Continued)
I/O Card
Pin
35
36
37
38
39
40
41
42
Signal Name
CLKOUT0
I2SIN_DOUT_A
I2SIN_CLK_A
I2SIN_DFS_A
I2C_SCL_B
I2C_SDA_B
SPI_NSS3_EZR
SPI_NSS2_EZR
Description
PB3.5 header
PB3.4 header
PB3.3 header
PB3.2 header
PB3.1 header
43
SPI_NSS1_EZR
44
SPI_NSS0_EZR
45
SPI_MOSI_EZR
46
SPI_MISO_EZR
47
SPI_SCK_EZR
48
UART_CTS_SYS
49
UART_RTS_SYS
50
UART_RX_SYS
51
GND
52
UART_TX_SYS
53
UART_CTS_A
54
UART_RTS_A
55
UART_RX_A
56
UART_TX_A
57
TIMER_EX_B
58
TIMER_CT_B
59
TIMER_EX_A
60
TIMER_CT_A
61
I2C_SCL_EZR
62
I2C_SDA_EZR
63
I2SOUT_DOUT_A
64
I2SOUT_CLK_A
65
I2SOUT_DFS_A
66
PCA_CH1_B
67
PCA_CH0_B
68
PCA_ECI_B
69
PCA_CH1_A
70
PCA_CH0_A
71
PCA_ECI_A
PB3.0 header
PB0.8 header
PB0.7 header
PB0.6 header
PB0.5 header
PB1.15 header
PB1.14 header
PB1.13 header
PB1.12 header
PB4.5 header
PB4.4 header
PB4.3 header
PB4.2 header
PB1.11 header
PB1.2/TRST header
PB1.1 header
PB0.14 header
PB0.14 header
PB0.13 header
16
Rev. 0.1